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What’s happening with 450mm: G450C update and status 16 Aug 2013 | 04:17 pm
The Global 450mm Consortium (G450C) has been driving the effective industry 450mm development. It is co-ordinating test wafer capability supporting development and demonstrating unit process tool perf...
300mm is the new 200mm! 15 Aug 2013 | 12:10 am
300mm is the new 200mm, said GlobalFoundries’ David Duke, during a presentation titled ‘Used Equipment Market’ at the recently held Semicon West 2013 in San Francisco, USA. Used semiconductor equipmen...
Welcome to the converged infrastructure! 2 Aug 2013 | 10:11 am
Don’t want to miss deadlines? Feel challenged about resources to deliver on critical business issues/initiatives? Well, are you desirous of responding much, much faster to customer requirements? Welco...
Xilinx tapes-out first UltraScale ASIC-class programmable architecture 19 Jul 2013 | 11:47 am
Xilinx Inc. has taped-out the first 20nm All Programmable Device with first UltraScale ASIC-class programmable architecture. It is said to be the semiconductor industry’s first 20nm device, and the PL...
EC’s goal: Reach 20 percent share in chip manufacturing by 2020! 12 Jun 2013 | 03:53 pm
The European Commission is said to have a goal: to reach 20 percent world-share in chip manufacturing by 2020! Heinz Kundert, president, SEMI Europe, has even laid out an industrial strategy that will...
Moore’s Law good for 14nm, and probably, 10nm: Dr. Wally Rhines 31 May 2013 | 05:02 am
Its a pleasure to talk to Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. On his way to DAC 2013, where he will be giving a ten-minute “Visionary Talk”, he found time to speak wi...
Global semiconductor companies delivering platforms: Jaswinder Ahuja, Cadence 28 May 2013 | 07:30 pm
Some time ago, Cadence Design Systems Inc. had announced the EDA360 vision! As per Jaswinder Ahuja, corporate VP and MD of Cadence Design Systems India, the Cadence vision of EDA360 is said to be well...
Cadence Tempus accelerates timing analysis and closure by weeks! 24 May 2013 | 02:00 pm
Cadence Design Systems Inc. has announced the Tempus timing signoff solution. It facilitates ground-breaking signoff timing analysis and closure. The new technology accelerates timing analysis and clo...
Semicon in sub-20nm era: Business as usual or different? 21 May 2013 | 09:00 pm
We are now entering the sub-20nm era. So, will it be business as usual or is it going to be different this time? With DAC 2013 around the corner, I met up with John Chilton, senior VP, Marketing and S...
Agnisys makes design verification process extremely efficient! 20 May 2013 | 05:02 am
Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification to...
